library ieee;
use ieee.std_logic_1164.all;
use work.mis_componentes.all;


entity multi4bits is
		port( a:in std_logic_vector(3 downto 0);
			  b:in std_logic_vector(3 downto 0);
			  p:out std_logic_vector(7 downto 0));
end multi4bits;

architecture multi of multi4bits is
signal m00:std_logic;
signal m01:std_logic;
signal m02:std_logic;
signal m03:std_logic;
signal m10:std_logic;
signal m11:std_logic;
signal m12:std_logic;
signal m13:std_logic;
signal m20:std_logic;
signal m21:std_logic;
signal m22:std_logic;
signal m23:std_logic;
signal m30:std_logic;
signal m31:std_logic;
signal m32:std_logic;
signal m33:std_logic;
signal s: std_logic_vector(11 downto 0);
signal c: std_logic_vector(11 downto 0);
begin

m00<=a(0) and b(0);
m01<=a(0) and b(1);
m02<=a(0) and b(2);
m03<=a(0) and b(3);

m10<=a(1) and b(0);
m11<=a(1) and b(1);
m12<=a(1) and b(2);
m13<=a(1) and b(3);


m20<=a(2) and b(0);
m21<=a(2) and b(1);
m22<=a(2) and b(2);
m23<=a(2) and b(3);


m30<=a(3) and b(0);
m31<=a(3) and b(1);
m32<=a(3) and b(2);
m33<=a(3) and b(3);


p(0)<=m00;
S0:sum1bit PORT MAP(a=>m01,b=>m10,Cin=>'0',s=>s(0),Cout=>c(0));
p(1)<=s(0);

S1:sum1bit PORT MAP(a=>m02,b=>m11,Cin=>'0',s=>s(1),Cout=>c(1));
S2:sum1bit PORT MAP(a=>s(1),b=>m20,Cin=>c(0),s=>s(3),Cout=>c(3));
p(2)<=s(3);

S3:sum1bit PORT MAP(a=>m03,b=>m12,Cin=>'0',s=>s(2),Cout=>c(2));
S4:sum1bit PORT MAP(a=>s(2),b=>m21,Cin=>c(1),s=>s(4),Cout=>c(4));
S5:sum1bit PORT MAP(a=>s(4),b=>m30,Cin=>c(3),s=>s(6),Cout=>c(6));
p(3)<=s(6);

S6:sum1bit PORT MAP(a=>m13,b=>m22,Cin=>c(2),s=>s(5),Cout=>c(5));
S7:sum1bit PORT MAP(a=>s(5),b=>m31,Cin=>c(4),s=>s(7),Cout=>c(7));
S8:sum1bit PORT MAP(a=>s(7),b=>'0',Cin=>c(6),s=>s(9),Cout=>c(9));
p(4)<=s(9);


S9:sum1bit PORT MAP(a=>m23,b=>m32,Cin=>c(5),s=>s(8),Cout=>c(8));
S10:sum1bit PORT MAP(a=>s(8),b=>c(9),Cin=>c(7),s=>s(10),Cout=>c(10));
p(5)<=s(10);

S11:sum1bit PORT MAP(a=>m33,b=>c(10),Cin=>c(8),s=>s(11),Cout=>c(11));
p(6)<=s(11);

p(7)<=c(11);

end multi;